1. Field of the Invention
The present invention relates generally to a nonvolatile memory device and, more particularly, to a nonvolatile memory device which has a multi-layer of block oxide layers to increase a coupling ratio instead of conventional oxide-nitride-oxide(hereinafter referred to as “ONO”) structure.
2. Background of the Related Art
In general, there are two categories in semiconductor devices, namely, a volatile memory and a non-volatile memory. The volatile memory again includes a dynamic random access memory (hereinafter referred to as “DRAM”) and a static DRAM (hereinafter referred to as “SDRAM”). One characteristic of the volatile memory is that data are maintained just while electric power is being applied. In other words, when power is turned off, the data in the volatile memory disappear. On the other hand, the non-volatile memory, mainly a ROM (Read Only Memory), can keep the data regardless of the application of electric power.
From the point of a view of the fabrication process, the non-volatile memory is divided into a floating gate type and a metal insulator semiconductor (hereinafter referred to as “MIS”) type. The MIS type has doubly or triply deposited dielectric layers which comprise at least two kinds of dielectric materials.
The floating gate type stores data using potential wells, and is represented by an ETOX (Electrically erasable programmable read only memory Tunnel OXide) used in a flash EEPROM (Electrically Erasable Programmable Read Only Memory).
The MIS type performs the program operation using traps at a bulk dielectric layer, an interface between dielectric layers, and an interface between a dielectric layer and a semiconductor. A Metal/Silicon ONO Semiconductor (hereinafter referred to as “MONOS/SONOS”) structure mainly used for the flash EEPROM is a representative MIS structure.
A conventional SONOS memory device comprises a tunnel oxide layer, a trap nitride layer and a block oxide layer on a P-type silicon substrate, and a gate deposited thereon.
In the SONOS memory device, a program operation is performed by fowler-nordheim (hereinafter referred to as “FN”) tunneling or directly tunneling electrons so that the electrons are trapped at a predetermined site in the trap nitride layer, thereby increasing a threshold voltage. An erase operation also moves the electrons by various tunneling ways such as the FN tunneling, the direct tunneling, and trap assisted tunneling so that the electrons are withdrawn to the P-type silicon substrate, thereby decreasing the threshold voltage.
Because the conventional SONOS device has employed the tunneling method for both the program and erase operations as described above, the thickness of the tunnel oxide has to be at most about 20 Å to achieve an adequate program/erase operating speed. However, the thin thickness of the tunnel oxide may detrimentally affect the retention characteristic of the memory device. Thus, various methods have been provided to solve such a problem in the SONOS device. One known method is to thicken the tunnel oxide layer, employ a thermal electron injection to perform the program operation, and a hot hole injection to perform the erase operation, thereby improving the retention characteristic. However, the above-described method radically deteriorates the endurance characteristic of the SONOS device.
FIG. 1 is a cross-sectional view illustrating a conventional floating gate of a single bit stack gate type.
Referring to FIG. 1, a tunneling oxide layer Comprising an SiO2 layer 14 is formed on a P-type silicon substrate 11. A polysilicon floating gate 15 is formed on the tunneling oxide layer of the resulting structure. An oxide-nitride-oxide (hereinafter referred to as “ONO”) layer 16 is formed to increase the coupling ratio. A control gate 17 is formed on the ONO layer 16. A source 13 and a drain 12 are then made adjacent to the both sides of the bottom of the SiO2 layer 14.
FIG. 2 is a graph illustrating the threshold voltage distribution of the program/erase operations of the conventional floating gate of a single bit stack gate type.
Referring to FIG. 2, the threshold voltage of a cell 18 can become under 0[V] by an over-erase during the erase operation. In that case, the threshold distribution of the erase operation is wider than that of the program operation, thereby decreasing a threshold voltage window. In other words, even just one over-erased cell in the bit line may induct excessive current into the bit line and, therefore, interrupt reading data of other cells along the bit line. Such over-erase may be caused by various structural problems such as a critical dimension in the cell of the flash memory, the thickness of the tunneling oxide layer, a junction overlap, the critical dimension of the floating gate, unevenness of the surface of the floating gate, the thickness of the ONO layer, the damage of the tunneling oxide layer, locally thin tunneling oxide layer, and pin holes. A well-known conventional method for solving the over-erase problem comprises the steps of detecting an over-erased cell, and reprogramming the detected over-erased cell in order to increase the threshold voltage thereof.
However, detecting the over-erased cell is a time-consuming job and, additionally, complicated circuits are required to recover the detected over-erased cell. Moreover, the threshold voltage distribution during the erase operation is wide and affects the threshold voltage distribution of a later program operation. Consequently, the threshold voltage window decreases and a multi-level bit is difficult to achieve in accordance with the conventional art methods.